Deep neural networks have made significant advancements in generative AI. However, their architecture poses a hurdle to achieving optimal efficiency. Traditional neural networks have separate units for memory and processing, leading to increased demands for communication between these components, resulting in slower speeds and reduced efficiency. IBM Research sought to overcome this hurdle by taking inspiration from the human brain, known for its remarkable performance and low power consumption. In a recent paper titled "A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference, " published in Nature Electronics, IBM researchers presented a new approach to develop a state-of-the-art mixed-signal AI chip that improves efficiency and minimizes battery drain in AI projects. The chip features 64 analog in-memory cores, each hosting an array of synaptic cell units that interact similarly to synapses in the brain. Smooth transitions between analog and digital states are ensured by converters. IBM reported that the chips achieved an accuracy rate of 92. 81% on the CIFAR-10 dataset, a widely used collection of images for machine learning training. The researchers also demonstrated near-software-equivalent inference accuracy with ResNet and long short-term memory networks.

To achieve end-to-end improvements in latency and energy consumption, the mixed-signal chip must be combined with on-chip digital operations and on-chip communication, according to the researchers. They developed a multicore mixed-signal chip fabricated using 14 nm complementary metal–oxide–semiconductor technology with phase-change memory integration. With these advancements, large and complex workloads can be executed in low power or battery-constrained environments such as cellphones, cars, and cameras. Additionally, cloud providers can leverage these chips to reduce energy costs and their carbon footprint. Future improvements in digital circuitry will allow the execution of fully pipelined end-to-end inference workloads on these chips by enabling layer-to-layer activation transfers and intermediate activation storage in local memory. The successful silicon validation of these components marks a significant milestone in the field of Analog-AI, as discussed by the IBM researchers in a technical overview of the chip. They described the chip as the first fully integrated mixed-signal in-memory compute chip based on back-end integrated phase-change memory in a 14-nm complementary metal-oxide-semiconductor process. The chip comprises 64 AIMC cores, each with a memory array of 256x256 unit cells and a total of over 16M devices. Alongside the analog memory array, each core contains a light digital processing unit responsible for activation functions, accumulations, and scaling operations.