The proverbial saying "time is money" is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot be tested yet. The slower the test throughput, the more automatic test equipment (ATE) is needed to meet production demands. This poses a significant challenge for chip producers, as advancements in technology have led to higher pin counts, faster interfaces, and larger pattern memory, resulting in a drastic increase in the price of ATE hardware. Additionally, the increasing complexity and functionality of today's chips require more patterns, tester memory, and overall cost. These additional patterns also lead to longer tester runtimes, which in turn requires more testers to maintain throughput. Automatic test pattern generation (ATPG) is universally used to generate programs for production testers. However, the complex nature of modern chips often results in lengthy runtimes for tests, causing delays in the start of production tests. For high-volume products where millions of chips will go through testing, even a slight reduction in test time can yield significant benefits. However, any reduction in patterns must maintain high test coverage to ensure the quality of parts shipped to customers. Therefore, an effective and efficient ATPG solution must meet high requirements for both the generated test programs and the generation process. The traditional pattern generation flow involves iteratively adjusting ATPG tool parameters to achieve desired results. This manual process requires expertise and multiple attempts to fine-tune tool settings, making it highly complex and time-consuming. Furthermore, it does not guarantee repeatability from design to design, leading to unpredictability in turnaround time and test pattern sign-off schedules.

Introducing artificial intelligence (AI) offers an innovative solution to meet the requirements of a modern pattern generation flow. An AI-based ATPG solution can intelligently learn about design characteristics, ATPG engine behavior, user constraints/targets, and available settings through parallel runs. By correlating results and refining settings, AI can achieve test coverage goals without manual iterations or manipulation of settings, resulting in first-time-right results. The recommended flow is to use standard ATPG for initial runs to achieve a clean design, followed by distributed ATPG runs to analyze, optimize, and validate target test coverage with fast runtimes. Once desired test coverage is achieved, AI can minimize test patterns before production testing. This flow enables a fast turnaround time, high-quality, and cost-efficient tester-ready patterns while maintaining the design schedule. Synopsys TSO. ai (Test Space Optimization) is an AI-driven ATPG solution that learns and tunes settings to consistently produce the smallest number of test patterns, eliminating unnecessary iterations and accelerating time-to-results for any design. In some cases, it has also achieved higher test coverage with a fixed pattern count when tester memory is limited. This technology can be used to minimize patterns for both the final tape-out netlist and designs already in production, quickly saving test costs. Additionally, it can learn throughout the design process with netlist drops, reducing the turnaround time of the final pattern reduction process. This approach has consistently resulted in a test cost reduction across all application segments, with typical pattern count reductions of 20% to 25% and more than 50% in some cases. This accelerates production tests, saving time and cost, while reducing the number of testers needed for a given production volume. Within the automotive ecosystem, an increasing number of standards and regulations aim to save development costs by protecting against cyberattacks. The first systems are planned for production in 2025, with hyper-NA to follow in the next decade.